1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory cell array and a process for producing the same and, particularly, to a semiconductor nonvolatile memory cell array composed of semiconductor nonvolatile memory cells that have simple memory operations and are produced at low costs.
2. Description of the Related Art
The semiconductor nonvolatile memory, which needs no power to retain stored information, is used as a memory for a low power device, such as a cell phone. A structure having a metal oxide nitride oxide semiconductor (MONOS) type memory cell with at least two gate electrodes has been proposed. See U.S. Pat. Nos. 5,408,115 and 6,255,166. The MONOS type memory cell has in the channel forming region a transistor with a gate insulating film or layer made of an oxide nitride oxide (ONO) laminated insulating film or layer in which charge can accumulate in addition to a transistor with an ordinary gate insulating film.
However, in the above semiconductor nonvolatile memory, it is necessary to optimize the respective channel densities in the channel forming regions formed under the ONO laminated insulation layer and the gate insulation layer. Where separate voltages are applied to the two gate electrodes, the corresponding peripheral circuits, such as voltage generators and decoders, are required, resulting in the complicated structure. In addition, the mechanism for operating the memory becomes complicated, and it is difficult to inject charge into the ONO laminated insulation layer in simple and effective manner. Since the memory has at least two gate electrodes and the associated gate insulation layers including the ONO laminated insulation layers, the memory cell structure becomes so complex that the manufacturing cost becomes high.